Load driving circuit, display driver, display apparatus and semiconductor device

ABSTRACT

Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current&gt;the first current, the second current&gt;the fourth current.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. application Ser.No. 17/989,660, filed on Nov. 17, 2022, which claims priority under 35USC 119 from Japanese Patent application No. 2021-194370 filed on Nov.30, 2021. Each of the entirety of the above-mentioned patentapplications is hereby incorporated by reference herein and made a partof this specification.

BACKGROUND Technical Field

The invention relates to a load driving circuit generating a drivingcurrent (voltage) driving a load, a display driver including the loaddriving circuit, a display apparatus including the load driver, and asemiconductor device.

Description of Related Art

Currently, as a main display apparatus, a display apparatus of an activematrix driving type using liquid crystal or organic EL in a displaypanel is conventionally known.

In the display panel, on an insulating transparent substrate, such as aglass substrate, a plastic substrate, etc., multiple data linesrespectively extending in a vertical direction of a two-dimensionalframe and multiple gate lines respectively extending in a horizontaldirection of the two-dimensional frame are disposed to intersect eachother. In addition, a pixel part connected with the data line and thegate line is formed at each of the intersections between the data linesand the gate lines. Each pixel part includes a thin film transistor(TFT) switch and a pixel electrode, and when the TFT switch is turned ONby a gate signal supplied to the gate line, a gradation data signalsupplied to the data line is supplied to the pixel electrode via theTFT.

The display panel of a liquid crystal display apparatus is formed byencapsulating liquid crystal devices between a semiconductor substrateon which thin film semiconductor circuits are formed and an oppositesubstrate on which opposite electrodes are formed on the entire surface.In the liquid crystal display apparatus, gradation display is performedby controlling the transmittance of backlight provided on the backsurface of the display panel by using a liquid crystal applicationvoltage. Color display is realized by assigning three primary colors ofRGB to each pixel and synthesizing the three primary colors through byusing an LED backlight and a color filter together.

Meanwhile, the display panel of an organic EL display apparatus isformed by a semiconductor substrate on which thin film semiconductorcircuits and organic EL elements are formed for respective pixel parts.In each pixel part, a pixel circuit performing current conversion on agradation data signal supplied to the pixel electrode and supplying thecurrent to the organic EL element is formed. The organic EL displayapparatus performs gradation display by controlling the light emissionintensity of the organic EL element through the current supplied to theorganic EL element of each pixel part. The color display is realizedthrough light emitted by organic EL elements of three primary colors,i.e., RGB, assigned to each pixel, or through synthesis of the threeprimary colors achieved through the combination of a color filter andthe light emitted by a single-color organic EL element.

Together with the display panel, the display apparatus includes, as aload driving circuit driving the display panel as a load, a gate driverand a data driver as follows.

The gate driver supplies a horizontal scan signal to the gate line. Thehorizontal scan signal exerts control to turn on, in order, the TFTswitch at each pixel column unit.

The data driver generates a gradation signal having an analog voltagevalue corresponding to the luminance level of each pixel, and suppliesthe gradation signal, as a data pulse of one scan period unit, to thedata line.

FIG. 1 is a block diagram schematically illustrating a configuration ofan active matrix type display apparatus.

The display apparatus shown in FIG. 1 includes a display panel 150 and acontroller 130. The display panel 150 includes gate lines GL1 to GLrarranged in the horizontal direction on an insulating substrate, datalines DL1 to DLm arranged in the vertical direction, and pixel parts 154arranged in a matrix at the intersection parts between the respectivegate lines and data lines. On the display panel 150, a gate driver 110driving each gate line and a data driver 120, as a display driver,driving each data line are provided. The controller 130 adjusts theoutput timings of the gate driver 110 and the data driver 120.

The gate driver 110 is supplied with a signal group GS form thecontroller 130, and outputs a scan signal supplied to each gate linebased on the signal group GS. The data driver 120 is supplied with avideo data signal VDS including CLK, a control signal, and a video datasignal, etc., from the controller 130, and, based on the video datasignal VDS, outputs a gradation signal supplied to each data line.

It is noted that the data driver 120 is usually formed by using asilicon LSI, and is implemented to an end part of the display panel 150by using chip-on-glass (COG) or chip-on-film (COF). In the case wherethe data driver 120 is formed by multiple individual ICs, the video datasignal VDS corresponding to the data line and each responsible fordriving is supplied to each data driver IC from the controller 130. Inthe case where the data driver 120 is a single IC or formed by a limitednumber of ICs, the controller 130 may be built in the data driver 120.In such case, the signal group supplied from the outside to thecontroller 130 is directly supplied to the data driver 120.

Meanwhile, in recent years, the resolution of display panels has beenincreasing, and the wiring width as well as the wiring interval havebeen decreasing together with the decrease of the pixel pitch. As aconsequence, the risk of failure in a display panel is increased.

Therefore, in recent years, a demand for providing a function ofdetecting a display panel abnormality or failure after the gate driver,the data driver, and the controller are installed is increased. Also, ina display panel to be mounted in a vehicle, in order to avoid thesituation of a frozen display image, there is a demand for a function ofquickly detecting a display panel abnormality.

Therefore, a liquid crystal display apparatus in which a circuit thatdetects and determines a flaw or defective state of a display panel isbuilt in the data driver, and it does not require an external inspectionapparatus, has been proposed (see, for example, FIGS. 1 and 4 ofJapanese Patent Application Laid-open (JP-A) No. 2000-275610). Suchliquid crystal display apparatus includes a switching circuit for anormal operation mode and an inspection mode as well as a comparator,and is further provided with a determination circuit that determineswhether the display panel is normal or abnormal based on a comparisonresult of comparing, by the comparator, a signal voltage supplied to thedata line and a reference voltage set in advance, at the time of theinspection mode.

In the liquid crystal display apparatus disclosed in JP-A No.2000-275610, the voltage of the output end of an output amplifierincluded in the data driver is detected, while the data line of thedisplay panel is driven by the output amplifier. Therefore, it isparticularly difficult to detect, in a high sensitivity, an abnormality,such as a small-scale short circuit, generated between the data line andother wirings in the display panel.

In addition, the determination circuit (see, for example, FIG. 4 of JP-ANo. 2000-275610) of the liquid crystal display apparatus is formed by aresistor generating the reference voltage and the comparator. Therefore,the detection accuracy may be varied due to variations of the resistoror variations of a threshold voltage of a transistor forming thecomparator.

Moreover, a circuit operated by using the same power potential as thatof the output amplifier, that is, a voltage higher than the powerpotential of a logic circuit is adopted as the switching circuit or thedetermination circuit for the normal operation mode and the inspectionmode. Therefore, the chip size, as well as the cost, may be increased.

SUMMARY

An aspect of the disclosure provides a load driving circuit. The loaddriving circuit includes: an output amplifier, having a push-pulloutput-stage formed by a first output-stage transistor and a secondoutput-stage transistor having different conductivity types, andoutputting an output current output from the push-pull output-stage to aload; and a detection circuit, detecting a change of the output current.The detection circuit includes: a coupling circuit, respectivelygenerating a first current and a second current that are minor currentswith respect to a current flowing in one of the first output-stagetransistor and the second output-stage transistor, respectivelygenerating a third current and a fourth current that are mirror currentswith respect to a current flowing in an other of the first output-stagetransistor and the second output-stage transistor, coupling the firstcurrent and the third current at a first output node to output a voltagegenerated at the first output node as a first voltage, and coupling thesecond current and the fourth current at a second output node to outputa voltage generated at the second output node as a second voltage. Thecoupling circuit respectively generates the first to fourth currents, sothat, in a reference state in which the output current is stable withina predetermined range, the third current is greater than the firstcurrent and the second current is greater than the fourth current. Thedetection circuit detects, based on the first voltage and the secondvoltage output from the coupling circuit, whether the output current ischanged from the reference state or not.

A display driver according to another aspect of the disclosure includesk load driving circuits, k being an integer of 2 or more. The displaydriver outputs a determination signal, which indicates whether theoutput current is changed from the reference state or not, to outsidewhile respectively outputting k output currents output from the k loaddriving circuits to k data lines of a display panel.

A display apparatus according to yet another aspect of the inventionincludes the display driver.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram schematically illustrating a configuration ofan active matrix type display apparatus.

FIG. 2A is a circuit diagram illustrating a configuration of a loaddriving circuit 100 according to a first embodiment.

FIG. 2B is a diagram illustrating a determination operation of adetermination circuit 60 included in the load driving circuit 100.

FIG. 3 is a diagram illustrating an example of an abnormal currentdetection operation by using the load driving circuit 100.

FIG. 4A is a circuit diagram illustrating a configuration of a loaddriving circuit 100A according to a second embodiment.

FIG. 4B is a diagram illustrating a determination operation of thedetermination circuit 60 included in the load driving circuit 100A.

FIG. 5 is a circuit diagram illustrating a configuration of a loaddriving circuit 100B according to a third embodiment.

FIG. 6 is a circuit diagram illustrating a configuration of a couplingcircuit 50A according to a fourth embodiment.

FIG. 7 is a circuit diagram illustrating a configuration of a couplingcircuit 50B as a modified example of the coupling circuit 50A.

FIG. 8 is a block diagram illustrating a configuration of a displayapparatus provided with a data driver 120_1 including the load drivingcircuit 100B.

FIG. 9 is a block diagram illustrating a configuration of the datadriver 120_1.

FIG. 10 is a timing chart illustrating an example of the timing forperforming abnormal current detection of a data line in the data driver120_1.

DESCRIPTION OF THE EMBODIMENTS

The invention provides a load driving circuit capable of suppressing theincrease in device scale, and sensitively, accurately, and quicklydetecting the abnormality of a current output to a load to drive theload, a display driver including multiple load driving circuits, adisplay panel including the display driver, and a semiconductor device.

According to the invention, by adopting a simple configuration of adetection circuit without using a resistor or a comparator, theabnormality of a current output to the load can be quickly, accurately,and sensitively detected without increasing the device scale.

Embodiment 1

FIG. 2A is a circuit diagram illustrating a configuration of a loaddriving circuit 100 according to a first embodiment of the invention.

The load driving circuit 100 shown in FIG. 2A is formed in asemiconductor IC chip as a semiconductor device, and is a circuit fordriving a capacitive load 90 such as a data line of a liquid crystaldisplay panel or an organic EL display panel. It is noted that a loadcomponent other than the display panel or a load circuit such as anelectric circuit realizing various functions may also serve as the load90.

The load driving circuit 100 includes a load driving voltage generationcircuit VGC, an output amplifier 10, and a detection circuit 40. Theload driving voltage generation circuit VGC, the output amplifier 10,and the detection circuit 40 receive a load driving power potential AVDDvia an AVDD power terminal as well as a load driving ground potentialAVSS via an AVSS power terminal.

The load driving voltage generation circuit VGC generates a drivingvoltage AMPIN having a voltage value for driving the load 90, andsupplies the driving voltage AMPIN to the output amplifier 10. Theoutput amplifier 10 outputs an output current to the load 90 connectedto an output terminal P1 via the output terminal P1, so that the voltageof the output terminal P1 is equal to the driving voltage AMPIN.

The detection circuit 40 detects whether the output current transmittedby the output amplifier 10 to the capacitive load 90 is in an outputstable state. That is, since the voltage of the output end of the outputamplifier 10 is consistent with the voltage value corresponding to thedriving voltage AMPIN, the detection circuit 40 detects whether theoutput current is changed from a stable state (referred to as “referencestate” in the following) within a predetermined range close to zero,including a state in which the output current is zero. The detectioncircuit 40 outputs a determination signal JD indicating that the outputcurrent is abnormal in the case where a change from the reference state(output stable state) in the output current is detected and that theoutput current is normal in the case where such change is not detected.

The output amplifier 10 has a push-pull output-stage and a differentialstage 15. The push-pull output-stage is formed by a Pch transistor 11(referred to as “Pch” in the following) and an Nch transistor 12(referred to as “Nch” in the following) as a first transistor and asecond transistor whose conductivity types are different from eachother.

The differential stage 15 is an operational amplifier that receives thedriving voltage AMPIN by using its own non-inverting input end (+) andreceives the voltage (referred to as “output voltage”) of the outputterminal P1 by using its own inverting input terminal (−).

The differential stage 15 generates signals PG and NG having levelscorresponding to the difference between the driving amplifier AMPIN andthe output voltage. That is, the different stage 15 generates the signalPG whose level is lower as the driving voltage AMPIN is higher than theoutput voltage and the difference is greater, and generates the signalNG whose level is higher as the driving voltage AMPIN is lower than theoutput voltage and the difference is greater. The differential stage 15supplies the signal PG to the gate of the transistor 11 via a node n1,and supplies the signal NG to the gate of the transistor 12 via a noden2.

The source of the transistor 11 serving as a push-pull output-stage(referred to as the output-stage transistor 11) is applied with the loaddriving power potential AVDD, and the drain of the transistor 11 isconnected to a node n0, the output terminal P1, and the drain of thetransistor 12. The source of the output-stage transistor 12 is appliedwith the ground potential AVSS. The output-stage transistor 11 transmitsthe output current corresponding to the signal PG received by its owngate to the node n0 via its own drain.

The source of the transistor 12 serving as a push-pull output-stage(referred to as the output-stage transistor 12) is applied with the loaddriving ground potential AVSS, and the drain of the transistor 12 isconnected to the output terminal P1 and the drain of the transistor 11.The output-stage transistor 12 extracts the output current correspondingto the signal NG received by its own gate from the node n0.

At the push-pull output-stage, when one of the current (chargingcurrent) transmitted by the output-stage transistor 11 to the outputterminal P1 based on the power potential AVDD and the current(discharging current) extracted by the output-stage transistor 12 fromthe output terminal P1 to the terminal side of the ground potential AVSSgenerates an increasing effect, the other generates a decreasing effect.That is, a push-pull operation is performed.

According to the above configuration, the output current obtained bysubtracting the discharging current from the charging current istransmitted to the load 90 via the node n0 and the output terminal P1.Accordingly, an output driving signal having the driving voltage AMPINis generated at the node n0, and the load 90 is driven by the outputdriving signal.

The detection circuit 40 includes an active/inactive switching circuit20, a coupling circuit 50, and a determination circuit 60.

The active/inactive switching circuit 20 includes switches 21 and 23 setto one of the ON state and the OFF state complementary to each other andswitches 22 and 24 set to one of the ON state and the OFF statecomplementary to each other. The active/inactive switching circuit 20receives a control signal CNT that prompts various kinds of operationcontrol.

Here, in the case of receiving the control signal CNT that prompts toactivate the detection circuit 40, the active/inactive switching circuit20 sets the switches 21 and 22 to the OFF state, and the switches 23 and24 to the ON state. Accordingly, the node n1 of the output amplifier 10is connected with a node n5 of the coupling circuit 50, the node n2 ofthe output amplifier 10 is connected with a node n6 of the couplingcircuit 50, and the detection circuit 40 becomes active (enabled) andperforms the detection operation of the output current to be describedafterwards.

Meanwhile, in the case of receiving the control signal CNT that promptsto deactivate the detection circuit 40, the active/inactive switchingcircuit 20 sets the switches 23 and 24 to the OFF state, and theswitches 21 and 22 to the ON state. Accordingly, the node n5 is appliedwith the load driving power potential AVDD, the node n6 is applied withthe load driving ground potential AVSS, and the connection between thenode n1 and the node n5 and the connection between the node n2 and thenode n6 are cut off together. Accordingly, the detection circuit 40becomes inactive (disabled), and the detection operation of the outputcurrent to be described afterwards is stopped.

Switches set to the ON state or the OFF state in association with theswitches 23 and 24 may be further provided between a node n7 and theAVSS power terminal and between a node n8 and the AVDD power terminal.

The coupling circuit 50 is formed by a Pch transistor 51 as the firsttransistor, a Pch transistor 52 as the second transistor, an Nchtransistor 53 as the third transistor, and an Nch transistor 54 as thefourth transistor. The source of each of the transistors 51 and 52 isapplied with the power potential AVDD, and the gate of each of thetransistors 51 and 52 is connected to the node n5. The drain of thetransistor 51 is connected to the drain of the transistor 53 via thenode n7. The drain of the transistor 52 is connected to the drain of thetransistor 54 via the node n8. The gate of each of the transistors 53and 54 is connected to the node n6, and the source of each of thetransistors 53 and 54 is applied with the ground potential AVSS.

With such configuration, in the coupling circuit 50, a first minorcurrent pair (I1, I3) with respect to the currents flowing in theoutput-stage transistors 11 and 12 of the output amplifier 10 isgenerated by using the transistors 51 and 53. In addition, a secondminor current pair (I2, I4) with respect to the currents flowing in theoutput-stage transistors 11 and 12 of the output amplifier 10 isgenerated by using the transistors 52 and 54.

That is, the transistor 51 generates the first current I1 of the sourcetype including a mirror current with respect to the current flowing inthe output-stage transistor 11, and the transistor 52 generates thesecond current I2 of the source type including a mirror current withrespect to the current flowing in the output-stage transistor 11. Thetransistor 53 generates the third current I3 of the sink type includinga mirror current with respect to the current flowing in the output-stagetransistor 12, and the transistor 54 generates the fourth current I4 ofthe sink type including a mirror current with respect to the currentflowing in the output-stage transistor 12.

Here, in the coupling circuit 50, the first current I1 and the thirdcurrent I3 are coupled at the node n7. That is, the first current I1 istransmitted to the node n7, and the third current I3 is extracted fromthe node n7. Accordingly, in the coupling circuit 50, the voltagegenerated at the node n7 is output as a first voltage O1.

In addition, in the coupling circuit 50, the second current I2 and thefourth current I4 are coupled at the node n8. That is, the secondcurrent I2 is transmitted to the node n8, and the fourth current I4 isextracted from the node n8. Accordingly, in the coupling circuit 50, thevoltage generated at the node n8 is output as a second voltage O2.

That is, the node n7 serves as the first output node of the couplingcircuit 50, and the node n8 serves as the second output node of thecoupling circuit 50.

It is noted that, for the transistors 51 to 54, transistors whosecurrent output capabilities are respectively set, so that in thereference state (output stable state) of the output current, the thirdcurrent I3 is greater than the first current I1, and the fourth currentI4 is smaller than the second current I2, are used.

The determination unit 60 receives the first voltage and the secondvoltage (O1, O2), and, based on the logic values of the first voltageand the second voltage, detects whether there is a change from thereference state (output stable state) with respect to the output currentof the output amplifier 10 and the tendency of the change. In addition,based on whether there is a detected change and the tendency of thechange, in the case where the determination circuit 60 determineswhether the output current of the output amplifier 10 is normal orabnormal and determines that the output current is abnormal, thedetermination circuit 60 determines that an abnormal current flows inone of the output-stage transistors 11 and 12. The determination circuit60 outputs a determination signal JD indicating the determinationresult. It is noted that the determination circuit 60 is formed in alogic circuit operated by using a power potential VDD and a groundpotential VSS for a logic circuit.

FIG. 2B is a diagram illustrating a determination operation of thedetermination circuit 60 based on the first voltage and the secondvoltage (O1, O2) in the load driving circuit 100 shown in FIG. 2A.

As shown in FIG. 2B, in the case where the binary logic values (L or H)represented by the first voltage O1 and the second voltage O2 aredifferent from each other, the determination circuit 60 outputs thedetermination signal JD indicating that the output current of the outputamplifier 10 is normal. Meanwhile, in the case where the logic valuesrepresented by the voltages O1 and O2 are equal, such as the case wherethe logic values are both the logic values L, the determination circuit60 outputs the determination signal JD indicating that there isabnormality in the output current output by the output-stage transistor12 of the output amplifier 10. Also, in the case where the logic valuesrepresented by the voltages O1 and O2 are both H, the determinationcircuit 60 outputs the determination signal JD indicating that there isabnormality in the output current output by the output-stage transistor11 of the output amplifier 10.

In the following, the operation of the load driving circuit 100 shown inFIGS. 2A and 2B will be further described with details.

As shown in FIG. 2A, the voltages supplied to the sources and the gatesof the transistors 51 and 52 of the coupling circuit 50 and theoutput-stage transistor 11 are the same. Therefore, the transistors 51and 52 generate the mirror currents I1 and I2 corresponding to thecurrent flowing in the output-stage transistor 11. Likewise, thevoltages supplied to the sources and the gates of the transistors 53 and54 and the output-stage transistor 12 are the same. Therefore, thetransistors 53 and 54 generate the mirror currents I3 and I4corresponding to the current flowing in the output-stage transistor 12.In addition, the currents I1 and I3 generated by using the transistors51 and 53 form the first minor current pair with respect to the currentsflowing in the output-stage transistors 11 and 12. In addition, thecurrents I2 and I4 generated by using the transistors 52 and 54 form thesecond mirror current pair with respect to the currents flowing in theoutput-stage transistors 11 and 12.

The four currents I1, I2, I3, and I4 generated in the coupling circuit50 are formed by the source-type currents I1 and I2 mirroring thecurrent of the output-stage transistor 11 and the sink-type currents I3and I4 mirroring the current of the output-stage transistor 12. Thecoupling circuit 50 couples the source-type current I1 and the sink-typecurrent I3 at the first output end (node n7) and outputs the voltage O1,and couples the source-type current I2 and the sink-type current I4 atthe second output end (node n8) and outputs the voltage O2.

In the coupling circuit 50, the respective current output capabilitiesof the transistors 51 to 54 are set, so that, in the reference state ofthe output amplifier 10,

I1<I3 and I2>I4

among the currents I1, 12, 13, and 14.

Accordingly, in the reference state, the voltage of the first output end(node n7) of the coupling circuit 50 is at a low level (AVSS), thevoltage of the second output end (node n8) is at a high level (AVSS),and the logic values of the output voltages (O1, O2) is (L, H).

Here, in the case where an abnormal current flows from the outputamplifier 10 to the load 90, the current of one of the output-stagetransistors 11 and 12 increases, and the current of the other decreases.In this case, the voltages (O1, O2) output from the coupling circuit 50becomes (L, L) or (H, H).

The determination circuit 60 receives two voltages (O1, O2) output fromthe coupling circuit 50, and, based on the logic values of the voltages(O1, O2), determines whether the output current of the output amplifier10 is changed from the reference state and outputs the determinationsignal JD.

The determination circuit 60 performs determination based on the logicvalues of the output voltages (O1, O2) of the coupling circuit 50, asshown in FIG. 2B. The determination circuit 60 determines that theoutput current is in the reference state when the voltages (O1, O2) are(L, H). Meanwhile, when the voltages (O1, O2) are (L, L), thedetermination circuit 60 detects that the current of the output-stagetransistor 12 increases by a predetermined amount or more and determinesthat the output current is abnormal, and when the voltages (O1, O2) are(H, H), the determination circuit 60 detects that the current of theoutput-stage transistor 11 increases by a predetermined amount or moreand determines the output current is abnormal.

Then, in the coupling circuit 50, the setting of the magnitude of eachof the currents I1, I2, I3, and I4 in the reference state is described.

The ratio of the current values of the currents I1, I2, I3, and I4 inthe reference state can be set by using a channel width ratio of thetransistors 51, 52, 53, and 54, for example. At the time of thereference state as described above, currents (m·Io) respectively flowingin the output-stage transistors 11 and 12, that is, idling currents, areequal.

Here, the channel width of each of the transistors 51 to 54 is set asfollows in order to suppress the current consumption of the detectioncircuit 40.

For example, in the case where the output-stage transistor 11 is set asa transistor of a total channel width (m Wp) formed by connecting inparallel m (m being an integer of 1 or more) transistors having apredetermined channel width Wp, the channel width of each of thetransistors 51 and 52 is set to the channel width Wp. In addition, inthe case where the output-stage transistor 12 is set as a transistor ofa total channel width (m·Wn) formed by connecting in parallel mtransistors having a predetermined channel width Wn, the channel widthof each of the transistors 53 and 54 is set to the channel width Wn.Accordingly, each current of the detection circuit 40 is suppressed toone-mth of the current flowing in the output-stage transistors 11 and12.

Specifically, the channel widths of the transistors 51 and 54 arerespectively set as Wp and Wn, the channel width of the transistor 53 isset as Wn+ greater than Wn, and the channel width of the transistor 52is set as Wp+ greater than Wp.

Accordingly, the relationship among the magnitudes of the current valuesof the currents I1, 12,13, and 14 in the reference state can be set asfollows:

I1<I3 and I2>I4.

It is noted that, regarding the channel length, it is preferable thatthe channel lengths of transistors of the same conductivity type are thesame in order to match the threshold voltage.

In addition, regarding the setting of the magnitude of the currents I1and I3 and the magnitude of the currents I2 and I4, such magnitudes areset by taking into consideration the sensitivity and the accuracy fordetecting the change from the reference state in the currents flowing inthe output-stage transistors 11 and 12. That is, in the case where thecurrents of the output-stage transistors 11 and 12 are changed, and theactual currents I1 and I3 are changed by reversing the current magnituderelationship of I1<I3 in the reference state into I1>I3, or the actualcurrents I2 and I4 are changed by reversing the current magnituderelationship of I2>I4 in the reference state into I2<I4, the logicvalues of the voltages (O1, O2) are changed from the values in thereference state, and the output current is determined as abnormal by thedetermination circuit 60.

It is noted that, with respect to a slight change due to elementmanufacturing variation or the ambient temperature within apredetermined range, the amplitudes of the currents in the referencestate can be set within a range of the reference state by setting I1<I3and I2>I4.

In the following, the effects of the detection circuit 40 shown in FIG.2A will be described.

The detection circuit 40 adopts a configuration in which the mirrorcurrents of the currents flowing in the output-stage transistors 11 and12 forming the push-pull output-stage are generated, the minor currentsof the source type and the sink type are coupled, and the outputvoltages (O1, O2) are extracted from the coupling points thereof.

Therefore, in the case where an abnormal current flows from the outputamplifier 10 to the load 90, the current of one of the output-stagetransistors 11 and 12 increases, and the current of the other decreases.At the same time, the minor currents of the output-stage transistors 11and 12 generate the same current change. Therefore, even if a relativelylarge current difference is set in the currents I1 and I3 and thecurrents I2 and I4 in the reference state, in the case where an abnormalcurrent flows through, the output voltages (O1, O2) quickly transitionto the logical values (L, L) or (H, H) indicating the determinationresult.

Therefore, the influence of the transistor manufacturing variation onthe detection circuit 40 is reduced, and the detection circuit 40 iscapable of sensitively and accurately detecting an output currentabnormality in a quick response. It is noted that, in the detectioncircuit 40 shown in FIG. 2A, whether the current amounts of the currentsflowing in the output-stage transistors 11 and 12 are changed from thereference state is detected, and an analog/digital conversion circuitconverting the detection into a two-bit digital value is realized.

In the following, an example of an abnormal current detection operationby the load driving circuit 100 shown in FIG. 2A is described withreference to FIG. 3 .

In the example shown in FIG. 3 , the configuration of the load drivingcircuit 100 and the size of each transistor are the same as those shownin FIG. 2A. In addition, in the example shown in FIG. 3 , the load 90 isset as a data line (capacitive load) of the display panel, and the dataline of the load 90 is short-circuited with an adjacent load (or aperipheral wiring) 99 due to a crack, etc., generated in the displaypanel. Because of the short circuit, a current is discharged from thedata line of the load 90 to the adjacent data line or a power systemwiring via the short-circuited part. At this time, among the respectivecurrents of the output-stage transistors 11 and 12, the current of theoutput-stage transistor 11 is increased from the reference state, andthe current of the output-stage transistor 12 is decreased from thereference state. Accordingly, in the case where the detection circuit 40is activated, the currents I1 and I2 of the transistors 51 and 52minoring the current of the output-stage transistor 11 also increase,and the currents I3 and I4 of the transistors 53 and 54 minoring theoutput-stage transistor 12 decrease.

At this time, although the amplitude relationship among the currents I1to I4 in the reference state is as follows:

I1<13, 12>I4,

the relative amplitudes of the currents I1 and I3 are reversed asfollows due to the occurrence of the abnormal current:

I1>I3, and

the difference between the currents I2 and I4 further increases.Accordingly, the output voltages (O1, O2) of the coupling circuit 50become (H, H), and the determination circuit 60 outputs thedetermination signal JD indicating that the output current is abnormal.

In FIG. 3 , an example in which a current is discharged from the dataline of the load 90 to the data line of the adjacent load 99 via theshort-circuited part. However, in an example in which a current flows,in a reverse direction, to the data line of the load 90 via theshort-circuited part, compared with the case of the reference state, thecurrent of the output-stage transistor 11 decreases, and the current ofthe output-stage transistor 12 increases. At this time, in the couplingcircuit 50, the currents I3 and I4 increase, and the currents I1 and I2decrease. Therefore, the output voltages (O1, O2) of the couplingcircuit 50 become (L, L), and the determination circuit 60 outputs thedetermination signal JD indicating that the output current is abnormal.

It is noted that, differing from the load driving circuit 100 shown inFIG. 1 or 2A that assumes a capacitive load, in the case of a drivingcircuit in which the output amplifier 10 outputs a constant current tothe load 90 at the time of the reference state, such as a poweramplifier, the currents of the output-stage transistors 11 and 12 at thetime of the reference state are not the same. However, even in suchcase, the mirror ratio with respect to the currents of the output-stagetransistors 11 and 12 are adjusted, and by setting the current outputcapability of each of the transistors 51 to 54 so that the amplitudes ofthe currents I1, I2, I3, and I4 at the time of the reference state ofthe coupling circuit 50 are as follows:

I1<I3, I2>I4,

it is possible to detect the change (abnormal current) of the outputcurrent in the reference state.

In addition, in the load driving circuit 100, by providing theactive/inactive switching circuit 20 and activating the detectioncircuit 40 only during a predetermined detection operation period, thecurrent consumption of the detection circuit 40 can be suppressed to theminimum.

As explicated in the above, the load driving circuit 100 includes theoutput amplifier 10 and the detection circuit 40, the output amplifier10 includes the push-pull output-stage formed by the first output-stagetransistor 11 and the second output-stage transistor 12 of differentconductivity types, and the detection circuit 40 detects an abnormalityof the output current output by the output amplifier 10 to the load. Thedetection circuit 40 includes the coupling circuit 50 and thedetermination circuit 60 as follows.

That is, the coupling circuit 50 respectively generates the firstcurrent and the second current (I1, I2) that are minor currents withrespect to the current flowing in the first output-stage transistor 11,and respectively generates the third current and the fourth current (I3,I4) that are mirror currents with respect to the current flowing in thesecond output-stage transistor 12. In addition, the coupling circuit 50couples the first current (I1) and the third current (I3) at the firstoutput node (n7), and outputs the voltage generated at the first outputnode (n7) as the first voltage (O1). In addition, the coupling circuit50 couples the second current (I2) and the fourth current (I4) at thesecond output node (n8), and outputs the voltage generated at the secondoutput node (n8) as the second voltage (O2). It is noted that, in thecoupling circuit 50, the first current to the fourth current arerespectively generated, so that, at the time of the reference state inwhich the output current is stable within the predetermined range, thethird current (I3) is greater than the first current (I1), and thesecond current (I2) is greater than the fourth current (I4). Thedetermination circuit 60 detects whether the output current is changedfrom the reference state that is stable within the predetermined rangebased on the first voltage and the second voltage (O1, O2), and, in thecase of detecting a change, outputs the determination signal JDindicating that the output current is abnormal and, in the case of notdetecting a change, outputs the determination signal JD indicating thatthe output current is normal.

At this time, between the currents flowing in the first output-stagetransistor 11 and the second output-stage transistor 12 of the push-pullstage, if one of the currents increases, the other decreases.Accordingly, the voltage (O1) of the coupling point (n7) of the mirrorcurrents (I1 and I3) and the voltage (O2) of the coupling point (n8) ofthe minor currents (I2, I4), which serve as the basis for generating thedetermination signal JD, follow the output current output by the outputamplifier 10, and quickly transition to the logic value indicating thedetermination result (whether the current is abnormal or not).

Moreover, according to the configuration of the coupling circuit 50, theinfluences of the manufacture variation of the transistors respectivelygenerating the first to fourth currents (I1 to I4) are reduced.

Thus, according to the load driving circuit 100, compared with the casewhere the current abnormality is determined by using a resistor or acomparator, it is possible to sensitively, accurately, and quicklydetect the abnormality of the output current.

Embodiment 2

FIG. 4A is a circuit diagram illustrating a configuration of a loaddriving circuit 100A according to a second embodiment of the invention.

The load driving circuit 100A shown in FIG. 4A is formed by asemiconductor IC chip that is a semiconductor device, and includes theload driving voltage generation circuit VGC, the output amplifier 10,and a detection circuit 40A (including mirror current generation parts41 and 42).

The load driving voltage generation circuit VGC generates a drivingvoltage AMPIN having a voltage value for driving the load 90, andsupplies the driving voltage AMPIN to the output amplifier 10.

The output amplifier 10 and the detection circuit 40A shown in FIG. 4Areceive the power potential AVDD for load driving via the AVDD powerterminal, and receive the ground potential AVSS for load driving via theAVSS power terminal. In addition, the detection circuit 40A receives thepower potential VDD for the logic circuit via the VDD power terminal,and receives the ground potential VSS for the logic circuit via the VSSpower terminal. Although the ground potential AVSS for load driving andthe ground potential VSS for the logic circuit are generally configuredas a common potential, they may also be configured as different powerpotentials depending on the purpose of application.

The relationship among the magnitudes of the respective power potentialsis, for example, as follows:

AVSS≤VSS<VDD≤AVDD.

Although the minor current generation parts 41 and 42 are shown in aregion of a broken line indicating the output amplifier 10 in FIG. 4A,the mirror current generation parts 41 and 42 are components included inthe detection circuit 40A.

Like the configuration shown in FIG. 2A, the output amplifier 10includes the output transistors 11 and 12 as the push-pull output-stageand the differential stage 15 formed by the operational amplifier. Sincethe operation thereof is the same as that shown in FIG. 2A, thedescription thereof will be omitted.

The detection circuit 40A is a detection circuit in which the detectioncircuit 40 shown in FIG. 2A is operable by using the power for the logiccircuit, and includes the active/inactive switching circuit 20, acurrent folding part 30, the mirror current generation parts 41 and 42,the coupling circuit 50, and the determination circuit 60.

In the minor current generation part 41, the source is applied with thepower potential AVDD, and the gate is formed by a Pch transistor 13connected to the node n1. It is noted that the drain of the transistor13 is connected to the detection circuit 40A via a node n3.

In the minor current generation part 42, the source is applied with theground potential AVSS, and the gate is formed by an Nch transistor 14connected to the node n2. It is noted that the drain of the transistor14 is connected to the detection circuit 40A via a node n4.

The circuit configuration of the active/inactive switching circuit 20shown in FIG. 4A is the same as that shown in FIG. 2A. However, in theconfiguration shown in FIG. 4A, the switch 21 of the active/inactiveswitching circuit 20 is connected between the drain (node n4) of thetransistor 14 and the common gate (node n5) of the transistors 51 and52, and the switch 22 is connected between the drain (node n3) of thetransistor 13 and the common gate (node n6) of the transistors 53 and54. The switch 23 is connected between the VDD power terminal and thecommon gate (node n5) of the transistors 51 and 52, and the switch 24 isconnected between the VSS power terminal and the common gate (node n6)of the transistors 53 and 54.

When receiving the control signal CNT with an activating instruction,the active/inactive switching circuit 20 turns on the switches 21 and 22together, and turns off the switches 23 and 24 together. Accordingly,the drain of the transistor 13 forming the mirror current generationpart 41 is connected to the node n6 via the node n3 and the switch 22,and the drain of the transistor 14 forming the mirror current generationpart 42 is connected to the node n5 via the node n4 and the switch 21,and the detection circuit 40A becomes enabled.

Meanwhile, in the case of receiving the control signal CNT promptingdeactivation, the switches 21 and 22 are turned off together, and theswitches 23 and 24 are turned on together. Accordingly, the connectionof the drain of each of the transistor 13 forming the mirror currentgeneration part 41 and the transistor 14 forming the mirror currentgeneration part 42 with the coupling circuit 50 is cut off, and thedetection circuit 40A becomes disabled.

The current folding part 30 includes a Pch transistor 31 as a firstfolding transistor and an Nch transistor 32 as a second foldingtransistor. In the transistor 31, the source is applied with the powerpotential VDD for the logic circuit, and the gate and the drain areconnected to the node n5. In the transistor 32, the source is appliedwith the ground potential VSS for the logic circuit, and the gate andthe drain are connected to the node n6.

Like the coupling circuit 50 shown in FIG. 2A, the coupling circuit 50includes the Pch transistors 51 and 52, and the Nch transistors 53 and54. It is noted that, in the coupling circuit 50 shown in FIG. 4A,although the connection of the transistors 51 to 54 is the same as thatshown in FIG. 2A, the source of each of the transistors 51 and 52 isapplied with the power potential VDD for the logic circuit, and thesource of each of the transistors 53 and 54 is applied with the groundpotential VSS for the logic circuit.

The determination unit 60 receives the first voltage and the secondvoltage (O1, O2), and, based on the logic values of the first voltageand the second voltage, detects whether the output current of the outputamplifier 10 is changed from the reference state (output stable state).In addition, based on whether there is a detected change, thedetermination circuit 60 determines whether the output current of theoutput amplifier 10 is normal or abnormal. In the case where thedetermination circuit 60 determines that the output current is abnormal,the determination circuit 60 determines in which of the output-stagetransistors 11 and 12 the abnormal current flows. The determinationcircuit 60 outputs a determination signal JD indicating thedetermination result.

FIG. 4B is a diagram illustrating a determination operation of thedetermination circuit 60 based on the first voltage O1 and the secondvoltage O2 in the load driving circuit 100A shown in FIG. 4A.

As shown in FIG. 4B, in the case where binary logic values (L or H)represented by the first voltage O1 and the second voltage O2 aredifferent from each other, the determination circuit 60 outputs thedetermination signal JD indicating that the output current of the outputamplifier 10 is normal.

Meanwhile, in the case where the logic values represented by thevoltages O1 and O2 are equal, such as the case where the logic valuesare both the logic values L, the determination circuit 60 outputs thedetermination signal JD indicating that there is abnormality in theoutput current output by the output-stage transistor 11 of the outputamplifier 10. Also, in the case where the logic values represented bythe voltages O1 and O2 are both H, the determination circuit 60 outputsthe determination signal JD indicating that there is abnormality in theoutput current output by the transistor 12 of the output amplifier 10.

In the following, the operation of the load driving circuit 100A shownin FIGS. 4A and 4B will be further described with details. It is notedthat the load 90 and the output amplifier 10 are the same as those shownin FIG. 2A, and the detailed description about the operation thereofwill be omitted.

The mirror current generation parts 41 and 42 are provided between theAVDD and AVSS power terminals, like the output-stage transistors 11 and12. Meanwhile, the main configuration of the detection circuit 40A,except for the mirror current generation parts 41 and 42, can beprovided between power terminals different from the output-stagetransistors 11 and 12. In FIG. 4A, the current folding part 30, thecoupling circuit 50, and the determination circuit 60 are providedbetween the VDD power terminal receiving the power potential VDD and theVSS power terminal receiving the ground potential VSS.

In the transistor 13 forming the mirror current generation part 41, itsown gate, like the gate of the output-stage transistor 11, receives thesignal PG output from the differential stage 15, and outputs a mirrorcurrent Ia of the source type corresponding to the current output fromthe output-stage transistor 11 from its own drain to the node n3.

In the transistor 14 forming the mirror current generation part 42, itsown gate, like the gate of the output-stage transistor 12, receives thesignal NG output from the differential stage 15, and outputs a mirrorcurrent Ib of the sink type corresponding to the current flowing in theoutput-stage transistor 12 from the node n4 to the AVSS power terminalvia its own drain.

It is preferable that the mirror ratio of the mirror current pair (Ia,Ib) with respect to the currents of the output-stage transistors 11 and12 is set to be 1 or less. Accordingly, the current consumption of thedetection circuit 40A can be suppressed. Specifically, with respect tothe channel widths of the output-stage transistors 11 and 12, thechannel widths of the transistors 13 and 14 are set to be small. Here,in the case where the detection circuit 40A is active, the current Ia ofthe source

type generated by the mirror current generation part 41 is supplied tothe drain of the transistor 32 via the node n3 and the switch 22, and ismirrored to the currents I3 and I4 of the transistors 53 and 54 of thecoupling circuit 50. In the transistors 32, 53, and 54, the sources andthe gates form a current mirror in common connection. That is, thetransistor 32 forms a current folding part that folds the current Ia ofthe source type flowing in the mirror current generation part 41 andmirrors the current Ia to the currents 13 and 14 of the sink type.

The current Ib of the sink type generated by the mirror currentgeneration part 42 flows in the transistor 31 via the node n4 and theswitch 21, and is mirrored to the currents I1 and I2 of the transistors51 and 52 of the coupling circuit 50. In the transistors 31, 51, and 52,the sources and the gates form a current mirror in common connection.That is, the transistor 31 forms a current folding part that folds thecurrent Ib of the sink type flowing in the mirror current generationpart 42 and mirrors the current Ib to the currents I1 and I2 of thesource type.

The coupling circuit 50, like the transistors 31 and 32 forming thecurrent folding part, is formed by the four transistors 51, 52, 53, and54 between the VDD power terminal and the VSS power terminal. In thecoupling circuit 50 of FIG. 4A, like that of FIG. 2A, the node n7 towhich the drains of the transistors 51 and 53 are commonly connected isset as the first output end of the coupling circuit 50, and outputs thevoltage O1. In addition, the node n8 to which the drains of thetransistors 52 and 54 are commonly connected is set as the second outputend of the coupling circuit 50, and outputs the voltage O2.

In addition, regarding the setting of the magnitude of each of thecurrents I1, I2, I3, and I4 in the reference state in the couplingcircuit 50, the size of each of the transistors 51 to 54, for example,is determined so that

I1 <I3 and I2>I4

among the currents I1, I2, I3, and I4. The current output capability ofeach of the transistors 51 to 54 is set in correspondence with the sizeof each transistor.

Specifically, the channel widths of the transistors 51 and 54 arerespectively set as Wp and Wn, the channel width of the transistor 53 isset as Wn+ greater than Wn, and the channel width of the transistor 52is set as Wp+ greater than Wp.

That is, except for the power potential VDD and the ground potential VSSthat are supplied, the coupling circuit 50 shown in FIG. 4A has the sameconfiguration as the coupling circuit 50 of FIG. 2A. However, differingfrom the coupling circuit 50 shown in FIG. 2A, the currents I1 and I2 ofthe source type generated by the coupling circuit 50 of FIG. 4A aregenerated as the mirror currents with respect to the current of theoutput-stage transistor 12, and the currents I3 and I4 of the sink typeare generated as the mirror currents with respect to the output-stagetransistor 11.

In the configuration shown in FIG. 4A, the determination circuit 60 isalso provided between the VDD power terminal and the VSS power terminal.The determination circuit 60, like FIG. 2A, receives the two voltages(O1, O2) output from the coupling circuit 50, and, based on the logicvalues of the voltages (O1, O2), determines whether the output currentof the output amplifier 10 is changed from the reference state andoutputs the determination signal JD indicating the determination result.

However, compared with the determination circuit 60 of FIG. 2A, thecorresponding relationship between the place where an abnormal currentoccurs (the output-stage transistor 11, 12) and the states of the logicvalues for determining abnormality (State 2, State 3 of FIG. 4B) isreversed in the determination circuit 60 shown in FIG. 4A.

In this way, in the configuration shown in FIG. 4A, the mainconfiguration part of the detection circuit 40A, except for the mirrorcurrent generation parts 41 and 42, can be realized by using a powerpotential range (VDD to VSS) smaller than the power potential range(AVDD to AVSS) of the detection circuit 40 shown in FIG. 2A. Forexample, when used in a liquid crystal display apparatus, 18V and 0V arerespectively supplied for the power potential AVDD and the groundpotential AVSS for load driving, and 1.8V and 0V are supplied for thepower potential VDD and the ground potential VSS for the logic circuit.Accordingly, the transistors 31, 32, 51 to 54 and the switches 23, 24can be realized by using low breakdown voltage elements same as thelogic circuit. Therefore, it is possible to reduce the power consumptionand the area that is taken up.

Embodiment 3

FIG. 5 is a block diagram illustrating a configuration of a load drivingcircuit 100B according to a third embodiment of the invention.

The load driving circuit 100B shown in FIG. 5 is formed by asemiconductor IC chip that is a semiconductor device, and has aconfiguration including a detection circuit 40B with respect to multipleoutput amplifiers driving multiple loads (data line loads).Nevertheless, while not shown in FIG. 5 , the minor current generationparts 41 and 42 included in the detection circuit 40B are provided, inthe connection configuration shown in FIG. 4A, for each outputamplifier.

Specifically, as shown in FIG. 5 , the load driving circuit 100Bincludes output amplifiers 10_1, 10_2, 10_3, . . . , 10_k drivingmultiple loads (data line loads) 90_1, 90_2, 90_3, . . . , 90_k (k beingan integer of 2 or more) via output terminals P1, P2, P3, . . . , Pk. Itis noted that the configuration of each of the output amplifiers 10_1 to10_k is the same as the configuration of the output amplifier 10 shownin FIG. 4A.

In addition, in the detection circuit 40B, an active/inactive switchingcircuit 20B is used in place of the active/inactive switching circuit20.

The active/inactive switching circuit 20B includes the switches 23 and24 like the active/inactive switching circuit 20 shown in FIG. 4A.However, in the active/inactive switching circuit 20B, in place of theswitches 21 and 22 shown in FIG. 4A, selection switches 21_1 to 21_k and22_1 to 22_k are used.

In the following, the output amplifier 10_1 shown in FIG. 5 , as therepresentative of the respective output amplifiers 10, and circuitsrelating to the output amplifier 10_1 are described.

The output amplifier 10_1, like the output amplifier 10 shown in FIG. 4, includes the differential stage 15 and the output-stage transistors 11and 12.

In addition, the mirror current generation parts 41 and 42 (not shown inFIG. 5 ) generating the minor current pairs flowing in the output-stagetransistors 11 and 12 and the selection switches 21_1 and 21_2controlling (selecting) the supply of the mirror current pairs generatedby the mirror current generation parts 41 and 42 to the nodes n5 and n6are connected to the output amplifier 10_1.

In the load driving circuit 100B, the configuration is provided for eachoutput amplifier.

The nodes n5 and n6 are common nodes receiving the mirror current pairsfrom the mirror current generation parts 41 and 42 connected to each ofthe output amplifiers 10_1 to 10_k.

Here, when the detection circuit 40B is active, at the time when any setof the selection switches among the selection switches (21_1, 22_1),(21_2, 22_2), . . . , (21_k, 22_k) respectively connected to the outputamplifiers 10_1, 10_2, . . . , 10_k is turned on, whether the outputcurrent of the output amplifier 10 corresponding to the selectionswitches changes can be detected by using the detection circuit 40B.

The sink-type current supplied to the node n5 is converted into thesource-type currents I1 and I2 by using the transistors 31, 51, and 52in the current folding part 30 and the coupling circuit 50 in thedetection circuit 40B. Similarly, the current of the source typesupplied to the node n6 is converted into the sink-type currents 13 and14 by using the transistors 32, 53, and 54. The operations and thefunctions of the coupling circuit 50 and the determination circuit 60are the same as those in FIGS. 4A and 4B.

Each switch of the active/inactive switching circuit 20B is controlledby the control signal CNT, and the control for activating/deactivatingthe detection circuit 40B as well as the selection of the outputamplifier for detecting whether the output current changes are carriedout. Specifically, when the detection circuit 40B is instructed to beactive according to the

control signal CNT, the switches 23 and 24 are turned off, and a set ofthe selection switches among the selection switches (21_1, 22_1), (21_2,22_2), . . . , (21_k, 22_k) are controlled to be turned on. By shiftingthe timing of turning on each selection switch to carry out theselection, it is possible to detect, in order, the state of the outputcurrent of each of the output amplifiers 10_1 to 10_k. When thedetection circuit 40B is instructed to be inactive, the switches 23 and24 are both turned off, and the selection switches (21_1, 22_1), (21_2,22_2), . . . , (21_k, 22_k) are all turned off.

As described above, the load driving circuit 100B shown in FIG. 5includes the output amplifiers 10_1 to 10_k respectively andindividually driving the loads 90_1 to 90_k, and includes the detectioncircuit 40B of one system with respect to the output amplifiers 10_1 to10_k.

In the load driving circuit 100B, by using the active/inactive switchingcircuit 20B, it is possible to selectively detect the change of theoutput current of each output amplifier with respect to the outputamplifiers. At this time, in the load driving circuit 100B, the currentabnormality of each of the output amplifiers can be detected by usingthe detection circuit 40B of one common system. Therefore, the area thatis taken up can be reduced.

In addition, the current folding part 30, the coupling circuit 50, thedetermination circuit 60, and the switches 23 and 24 of theactive/inactive switching current 20B of the detection circuit 40B canbe formed by using the power potential range (VDD to VSS) of the logiccircuit lower than the power potential range (AVDD to AVSS) of eachamplifier, so it is possible to further reduce the area that is takenup. Where necessary, a clamping element in serial connection with eachselection switch may also be provided between the nodes n3 and n4 ofeach output amplifier and the nodes n5 and n6 of the detection circuit40B. The clamping element is provided so that the potentials of thenodes n5 and n6 of the detection circuit 40B, for example, are clampedwithin the power potential range for the logic circuit. For example, inthe case where the clamping element is provided between the nodes n3 andn4 of each output amplifier and each selection switch, each selectionswitch can also be formed in the power potential range (VDD to VSS) ofthe logic circuit.

Embodiment 4

FIG. 6 is a circuit diagram illustrating a configuration of a couplingcircuit 50A, which is another specific example of the coupling circuit50 shown in FIGS. 2A, 4A, and 5 .

In FIG. 6 , a voltage for generating the currents I1 and I2 of thesource type is supplied to the node n5, and a voltage for generating thecurrents I3 and I4 of the sink type is supplied to the node n6.

It is noted that, in the coupling circuit 50A, the current outputcapabilities of the respective transistors are set, so that, in thereference state of the output amplifier,

I1<I3 and I2>I4

are set for the respective currents I1, I2, I3, and I4.

The coupling circuit 50A includes the Pch transistor 51 outputting thecurrent I1 that is of the source type and in a fixed current amount andthe Nch transistor 54 outputting the current I4 that is of the sink typeand in a fixed current amount in the reference state, a circuit 52Aoutputting the current I2 of the source type in the reference state, anda circuit 53A outputting the current I3 of the sink type in thereference state. It is possible for the circuit 52A to adjust thecurrent amount of the current I2 based on a control signal CNTA, and itis possible for the circuit 53A to adjust the current amount of thecurrent I3 based on the control signal CNTA. Accordingly, it is possiblefor a detection circuit including the coupling circuit 50A to adjust aboundary value, that is, a detection sensitivity, at which the outputcurrent of the output amplifier 10 is switched from the reference state(output stable state) to the abnormal state, by using the control signalCNTA.

It is noted that the transistors 51 and 54 shown in FIG. 6 are the sameas the transistors 51 and 54 of the coupling circuit 50 shown in FIG.4A.

In the following, the circuits 52A and 53A are described.

The circuit 52A is in a configuration in which multiple sets of Pchtransistors and switches connected in series with each other areprovided in parallel between the VDD power terminal receiving the powerpotential VDD for the logic circuit and the node n8. In multiple Pchtransistors 52a_1, 52a_2, . . . , arranged in parallel, each source issupplied with the power potential VDD, each gate is commonly connectedto the node n5, and minor currents corresponding to the voltage of thenode n5 are respectively generated. Each of switches 57_1, 57_2, . . . ,arranged in parallel is controlled to be turned on and off based on acurrent ratio indicated in the control signal CNTA supplied from theoutside. At this time, among the switches 57_1, 57_2, . . . , asynthesis current of the transistor connected to the switch controlledto be turned on based on the current ratio is set as the current I2.That is, by variably setting the ratio of the Pch transistors 52a_1,52a_2, . . . , controlled to be active or inactive through the ON/OFFcontrol of the switches 57_1, 57_2, . . . , the current amount of thecurrent I2 with respect to the current I4 can be optimally adjusted.

The circuit 53A is in a configuration in which multiple sets of Nchtransistors and switches connected in series with each other areprovided in parallel between the VSS power terminal receiving the groundpotential VSS for the logic circuit and the node n7. In multiple Nchtransistors 53a_1, 53a_2, . . . , arranged in parallel, each source issupplied with the ground potential VSS, each gate is commonly connectedto the node n6, and minor currents corresponding to the voltage of thenode n6 are respectively generated. Each of switches 55_1, 55_2, . . . ,arranged in parallel is controlled to be turned on and off based on acurrent ratio indicated in the control signal CNTA supplied from theoutside. At this time, among the switches 55_1, 55_2, . . . , asynthesis current of the transistor connected to the switch controlledto be turned on based on the current ratio is set as the current I3.That is, by variably setting the ratio of the Nch transistors 53a_1,53a_2, . . . , controlled to be active or inactive through the ON/OFFcontrol of the switches 55_1, 55_2, . . . , the current amount of thecurrent I3 with respect to the current I1 can be optimally adjusted.

In the following, a specific example of setting the current outputcapability in each transistor shown in FIG. 6 is described.

For example, the current output capability of a Pch transistor which hasthe channel width Wp and in which the gate is connected to the node n5,and the current output capability of an Nch transistor which has thechannel width Wn and in which the gate is connected to the node n6 areequal.

The channel width of the Pch transistor 51 generating the current I1 ofthe source type of the coupling circuit 50A is set as Wp, and thechannel width of the Nch transistor 54 generating the current I4 of thesink type is set as Wn.

The circuit 52A generating the current I2 of the source type iscontrolled by the control signal CNTA, so that a synthesis currentequivalent to three Pch transistors of the channel width Wp isgenerated.

The circuit 53A generating the current I3 of the sink type is controlledby the control signal CNTA, so that a synthesis current equivalent tothree Nch transistors of the channel width Wn is generated.

Accordingly, the ratio among the current amounts of the respectivecurrents I1, I2, I3, and I4 in the reference state can be set asfollows:

I1:I3=1:3;

I2:I4=3:1.

Here, in the case where the difference between the ratio of the currentamount of the current I3 with respect to the current I1 and the ratio ofthe current amount of the current I2 with respect to the current I4 isset to be large, the boundary value for switching the output current ofthe output amplifier 10 to the abnormal state is increased. In addition,in the case where the difference between the ratios of the currentamounts is set to be small, the boundary value for switching the outputcurrent of the output amplifier 10 to the abnormal state is decreased.By adjusting the ratio of the current amount, it is possible tooptimally adjust the detection sensitivity.

FIG. 7 is a circuit diagram illustrating a configuration of a couplingcircuit 50B as a modified example of the coupling circuit 50A shown inFIG. 6 .

In the coupling circuit 50B, like the configuration shown in FIG. 6 ,the voltage for generating the currents I1 and I2 of the source type issupplied to the node n5, and the voltage for generating the currents I3and I4 of the sink type is supplied to the node n6.

In addition, in the coupling circuit 50B, the current outputcapabilities of the respective transistors are set, so that, in thereference state of the output amplifier,

I1<I3 and I2>I4

are set for the respective currents I1, I2, I3, and I4.

The coupling circuit 50B includes the Pch transistor 51 in which thecurrent I1 of the source type is set to a fixed value in the referencestate, the Nch transistor 54 in which the current I4 of the sink type isset to a fixed value in the reference state, and circuits 52B and 53Bcapable of individually making variable adjustment to the currentamounts of the current I2 of the source type and the current I3 of thesink type, respectively, in the reference state.

It is noted that the transistors 51 and 54 shown in FIG. 6 are the sameas the transistors 51 and 54 of the coupling circuit 50 shown in FIG.4A.

Here, the configurations of the circuits 52B and 53B are described inthe following.

The circuit 52B has a configuration in which the Pch transistor 52 and avariable current source 58 are provided in parallel between the VDDpower terminal receiving the power potential VDD for the logic circuitand the node n8.

In the transistor 52, the source is supplied with the power potentialVDD, the gate is connected to the node n5, and a mirror currentcorresponding to the voltage of the node n5 is generated.

In the variable current source 58, a current amount is controlled basedon a current ratio indicated in a control signal CNTB supplied from theoutside, and a current having the current amount flows between the VDDpower terminal and the node n8. Accordingly, a synthesis current of thetransistor 52 and the variable current source 58 is set as the currentamount of the current I2. That is, through the current control of thevariable current source 58, the difference between the current amount ofthe current I4 and the current amount of the current I2 can be setoptimally.

The circuit 53B has a configuration in which the Nch transistor 53 and avariable current source 59 are provided in parallel between the VSSpower terminal receiving the ground potential VSS for the logic circuitand the node n7.

In the transistor 53, the source is supplied with the ground potentialVSS, the gate is connected to the node n6, and a mirror currentcorresponding to the voltage of the node n6 is generated.

In the variable current source 59, a current amount is controlled basedon a current ratio indicated in the control signal CNT, and a currenthaving the current amount flows between a node n7 and the VSS powerterminal. Accordingly, a synthesis current of the transistor 53 and thevariable current source 59 is set as the current amount of the currentI3. That is, through the current control of the variable current source59, the difference between the current amount of the current I1 and thecurrent amount of the current I3 can be set optimally.

In the following, a specific example of setting the current outputcapability in the configuration shown in FIG. 7 is described.

For example, the current output capability of a Pch transistor which hasthe channel width Wp and in which the gate is connected to the node n5,and the current output capability of an Nch transistor which has thechannel width Wn and in which the gate is connected to the node n6 areequal. The channel width of the transistor 51 generating the current I1of the source type of the coupling circuit 50B is set as Wp, and thechannel width of the transistor 54 generating the current I4 of the sinktype is set as Wn. In the circuit 52B generating the current I2 of thesource type, the channel width of the transistor 52 is set as Wp. In thecircuit 53B generating the current I3 of the sink type, the channelwidth of the transistor is set as Wn.

Accordingly, the difference between the current amounts of the currentsI1 and I3 in the reference state is determined by the current amount ofthe variable current source 59, and the difference between the currentamounts of the currents I2 and I4 is determined by the current amount ofthe variable current source 58. In FIG. 7 as well, by adjusting theratio of the current amount of the current I3 with respect to thecurrent I1 and the ratio of the current amount of the current I2 withrespect to the current I4, it is possible to optimally adjust thedetection sensitivity, like FIG. 6 .

It is noted that, in each coupling circuit of FIGS. 6 and 7 , it ispreferable that the difference between the current amounts of thecurrents I1 and I3 in the reference state and the difference between thecurrent amounts of the currents I2 and I4 in the reference state are setso that slight changes due to the manufacture variation of eachtransistor, the ambient temperature within a predetermined range, etc.,fall within the range of the reference state.

In addition, in each coupling circuit in FIGS. 6 and 7 , although thetransistors 51 and 54 respectively generating the currents I1 and I4 aredescribed as individual transistors for the ease of description, thetransistors may also be configured by multiple transistors as long asthe ratio among the current amounts of the currents I1, I2, I3, and I4in the reference state can be set appropriately. In addition, the sizesof the respective transistors are not limited to those shown in FIGS. 6and 7 .

Embodiment 5

In the following, a specific example for the case in which the loaddriving circuit 100B shown in FIG. 5 is applied to the display apparatusis described.

FIG. 8 is a block diagram illustrating a configuration of a displayapparatus provided with a data driver 120_1 including the load drivingcircuit 100B.

The display apparatus shown in FIG. 8 includes the display panel 150 andthe controller 130. The display panel 150 includes the gate lines GL1 toGLr (r being an integer of 2 or more) arranged in the horizontaldirection on an insulating substrate, data lines DL1 to DLk (k being aninteger of 2 or more) arranged in the vertical direction, and the pixelparts 154 arranged in a matrix at the intersection parts between therespective gate lines and data lines. On the display panel 150, the gatedriver 110 driving each gate line and the data driver 120_1 driving eachdata line are provided, and the controller 130 adjusts the outputtimings of the gate driver 110 and the data driver 120_1.

The gate driver 110 is supplied with a signal group GS form thecontroller 130, and outputs a scan signal supplied to each gate linebased on the signal group GS.

The data driver 120_1 is supplied with the video data signal VDSincluding CLK, and various control signals and video data signals, etc.,from the controller 130, and, based on the video data signal VDS,outputs gradation signals supplied to the data lines DL1 to DLk.

It is noted that the data driver 120_1 is usually formed by using asilicon LSI, and is implemented to an end part of the display panel 150by using chip-on-glass (COG) or chip-on-film (COF). In the case wherethe data driver 120_1 is formed by multiple individual ICs, the videodata signal VDS including various control signals relating to data linesand each responsible for driving is supplied to each data driver IC fromthe controller 130. In the case where the data driver 120_1 is a singleIC or formed by a limited number of ICs, the controller 130 may be builtin the data driver 120_1. In such case, the signal group supplied fromthe outside to the controller 130 is directly supplied to the datadriver 120_1.

FIG. 9 is a block diagram illustrating an example of the internalconfiguration of the data driver 120_1.

As shown in FIG. 9 , the data driver 120_1 includes a control core part80, a timing control part 81, a data latch 82, a level shifter 83, agradation voltage generation part 84, a decoder 85, a multiplexer 86, anoutput amplification part 87, and the detection circuit 40B. Inaddition, the data driver 120_1 receives the power potential for thelogic circuit and the power potential for driving the data line (load)from the outside. The power potential for the logic circuit is suppliedto the control core part 80, the timing control part 81, the data latch82, and the detection circuit 40B, and the power potential for loaddriving is supplied to the level shifter 83, the gradation voltagegeneration part 84, the decoder 85, the multiplexer 86, and the outputamplification part 87.

The control core part 80 receives the video data signal VDS in serialarrangement supplied from the outside. The video data signal VDS is asignal including a clock CLK or various signal groups as well as settinginformation and is a serialized signal. The control core part 80 appliesa serial/parallel conversion process on the video data signal VDS, andextracts a series of video data PD, the clock CLK, the various signalgroups (a horizontal synchronization signal, a vertical synchronizationsignal, and various control signals), and the setting information fromthe video data signal VDS.

The control core part 80 generates a reference timing signal LOAD and apolarity reversing signal POL based on the horizontal synchronizationsignal and the vertical synchronization signal. The control core part 80supplies the clock CLK, the reference timing signal LOAD, and settinginformation SEI to the timing control part 81. In addition, the controlcore part 80 supplies the series of the video data PD, the settinginformation SEI, and the polarity reversing signal POL to the data latch82. In addition, the control core part 80 supplies gamma settinginformation STD to the gradation voltage generation part 84, suppliesthe polarity reversing signal POL to the multiplexer 86, and suppliesthe control signal CNT to the detection circuit 40B. In addition, thecontrol signal CNT may also include the control signal CNTA or CNTBcorresponding to the coupling circuit of FIG. 6 or 7 .

Based on the reference timing signal LOAD, the clock CLK, and thesetting information SEI, the timing control part 81 generates a latchoutput timing signal group controlling the timing of the gradationsignal output from each of the output terminals P1 to Pk of the datadriver 120_1 and supplies the latch output timing signal group to thedata latch 82.

For each output respectively corresponding to k pixels per horizontalscan line, the data latch 82 imports k video data PD from the series ofvideo data PD in accordance with the latch output timing group, andsupplies, as video data Q1 to Qk, the k video data PD to the levelshifter 83.

The level shifter 83 includes k level shifting circuits individuallyperforming level shifting on the amplitudes of the respective signallevels of the video data Q1 to Qk. The level shifting circuits generatedigital video data J1 to Jk with respect to the video data Q1 to Qk. Inthe digital data J1 to Jk, respective signal level amplitudes arelevel-shifted to a high amplitude that is greater.

The gradation voltage generation part 84, based on the gamma settinginformation STD and for the respective primary colors (red, green, blue)of pixels, generates multiple positive polarity gradation voltage groupsPOS and negative polarity gradation voltage groups NEG having voltagevalues in accordance with the gamma conversion characteristicscorresponding to the primary colors.

The decoder part 85 includes k decoders individually converting therespective digital video data J1 to Jk into analog voltage values. Thesek decoders use the positive polarity gradation voltage groups POS or thenegative polarity gradation voltage groups NEG, convert the respectivedigital video data J1 to Jk into positive or negative polarity analoggradation voltages corresponding to the luminance represented by a videodata piece, and supply the k analog gradation signals that are obtainedto the multiplexer 86.

The multiplexer 86 supplies, to the output amplification part 87, kanalog gradation signals in which the arrangement in the series of kanalog gradation signals, such as the exchange of the even-numbered onesand odd-numbered ones, is changed based on the polarity reversing signalPOL.

As shown in FIG. 5 , the output amplification part 87 includes theoutput amplifiers 10_1 to 10_k each having the circuit configuration(including 41 and 42) shown in FIG. 4A. The output amplifiers 10_1 to10_k respectively output k gradation signals in which the k analoggradation signals supplied from the multiplexer 86 are individuallyamplified to the data lines DL1 to DLk via the output terminals P1 toPk.

As shown in FIG. 5 , the detection circuit 40B includes theactive/inactive switching circuit 20B as well as the current foldingpart 30 and the coupling circuit 50 for one system and with the internalconfigurations shown in FIG. 4 .

The minor current generation parts 41 and 42 mirroring the currents ofthe output-stage transistors 11 and 12 are connected to the respectiveoutput amplifiers 10_1 to 10_k, the minor current pair selected, by theactive/inactive switching circuit 20B, from the minor current pairsgenerated by the respective mirror current generation parts istransmitted to the coupling circuit 50 of the detection circuit 40B, andwhether the output current changes with respect to the reference stateof the output amplifier is detected to determine whether the current isnormal or abnormal.

The active/inactive control with respect to the detection circuit 40Band the selection control of the active/inactive switching circuit 20Bis controlled through the control signal CNT from the control core part80. In addition, the determination signal JD of the detection circuit40B is supplied to the control core part 80. It is noted that, at thetime when the output current of the output amplifier is determined asabnormal by the detection circuit 40B, in the case of transmitting anabnormality detection notification to the user or stopping the displayapparatus, for example, it may also be that the control core part 80outputs a signal FB indicating such fact to an external controller basedon the determination signal JD.

It is noted that, if the above configuration is applied to the datadriver of an organic EL display apparatus, the polarity reversing signalPOL and the multiplexer 86 shown in FIG. 9 are omitted.

FIG. 10 is a timing chart illustrating an example of the timing forperforming abnormal current detection of a data line in the data driver120_1.

In FIG. 10 , the timing of one frame period from T0 to T1 correspondingto the re-writing period of one frame is shown. The one-frame period isdefined by the vertical synchronization signal (Vsyn). In a period fromT0 to t0 immediately after the one-frame period starts, there is ablanking period reflecting various setting signals. In a video dataactive period from t0 to tk after the blanking period, the analoggradation signals corresponding to the video data are output to datalines in one horizontal period (1H). In addition, according to the scansignal output from the gate driver 110, in the video data active periodfrom t0 to tk, gate lines are selected in order in association with thetiming (Hsyn) of one horizontal period, and the gate lines are set in anon-selected state in periods other than the data active period.

The detection circuit 40B mounted in the data driver 120_1 shown in FIG.8 is activated and performs a detection operation in an abnormalitydetection period from ta to tb during the blanking period from T0 to t0,for example. In the abnormality detection period from ta to tb, controlmay also be exerted so that the output amplifier connected to the dataline of the detection target is selected in order by the active/inactiveswitching circuit 20B. Alternatively, it may also be that the outputamplifiers selected in the abnormality detection period in one frameperiod are set as a limited number of output amplifiers, and for eachframe period, different output amplifiers are selected in order, andwhether there is an abnormal current is detected for all the data linesin multiple frame periods.

According to the data driver 120_1 shown in FIG. 8 , it is possible toprovide the data driver with a function of detecting malfunctioning of adisplay panel by detecting an abnormal current to the data line.

What is claimed is:
 1. A display driver, comprising a load drivingcircuit, the load driving circuit comprising: an output amplifier,having a push-pull output-stage formed by a first output-stagetransistor and a second output-stage transistor having differentconductivity types, and outputting an output current output from thepush-pull output-stage 5 to a load; and a detection circuit, detecting achange of the output current, wherein the detection circuit comprises: acoupling circuit, respectively generating a first current and a secondcurrent that are mirror currents with respect to a current flowing inone of the first output-stage transistor and the second output-stagetransistor, respectively generating a third current and a fourth currentthat are mirror currents with respect to a current flowing in an otherof the first output-stage transistor and the second output-stagetransistor, coupling the first current and the third current at a firstoutput node to output a voltage generated at the first output node as afirst voltage, and coupling the second current and the fourth current ata second output node to output a voltage generated at the second outputnode as a second voltage; wherein the coupling circuit respectivelygenerates the first to fourth currents, so that, in a reference state inwhich the output current is stable within a predetermined range, thethird current is greater than the first current and the second currentis greater than the fourth current, wherein the detection circuitdetects, based on the first voltage and the second voltage output fromthe coupling circuit, whether the output current is changed from thereference state or not, wherein the load driving circuit includes koutput amplifiers, k being an integer of 2 or more, wherein thedetection circuit: comprises a selection switch selecting, in order,each of k mirror current pairs respectively generated by the k outputamplifiers and respectively formed by a first mirror current withrespect to the current flowing in the one of the first output-stagetransistor and the second output-stage transistor and a second mirrorcurrent with respect to the current flowing in the other of the firstoutput-stage transistor and the second output-stage transistor,respectively generates the first current and the second current asmirror currents with respect to the first mirror current in the mirrorcurrent pair selected by the selection switch, and respectivelygenerates the third current and the fourth current as minor currentswith respect to the second mirror current in the minor current pairselected by the selection switch, and wherein the display driver outputsthe a determination signal, which indicates whether the output currentis changed from the reference state or not, to outside whilerespectively outputting k output currents output from the respective koutput amplifiers of the load driving circuit to k data lines of adisplay panel.
 2. A display apparatus, comprising the display driver asclaimed in claim
 1. 3. A semiconductor device, comprising: an outputamplifier, having a push-pull output-stage formed by a firstoutput-stage transistor and a second output-stage transistor havingdifferent conductivity types, and outputting an output current outputfrom the push-pull output-stage to a load; and a detection circuit,detecting a change of the output current, wherein the detection circuitcomprises: a coupling circuit, respectively generating a first currentand a second current that are mirror currents with respect to a currentflowing in one of the first output-stage transistor and the secondoutput-stage transistor, respectively generating a third current and afourth current that are mirror currents with respect to a currentflowing in an other of the first output-stage transistor and the secondoutput-stage transistor, coupling the first current and the thirdcurrent at a first output node to output a voltage generated at thefirst output node as a first voltage, and coupling the second currentand the fourth current at a second output node to output a voltagegenerated at the second output node as a second voltage; wherein thecoupling circuit respectively generates the first to fourth currents, sothat, in the reference state, the third current is greater than thefirst current and the second current is greater than the fourth current,and wherein the detection circuit detects, based on the first voltageand the second voltage output from the coupling circuit, whether theoutput current is changed from the reference state or not.
 4. Thesemiconductor device as claimed in claim 3, wherein the detectioncircuit further comprises a determination circuit, outputting, based onthe first voltage and the second voltage, a determination signalindicating that the output current is abnormal when the output currentis changed from the reference state and a determination signalindicating that the output current is normal when the output current isnot changed.